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High-Accuracy Parasitic Extraction1
Book chapter

High-Accuracy Parasitic Extraction1

Zhengfeng (Jeff) Wu and Ioannis Savidis
Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology, pp 744-768
2026
DOI: https://doi.org/10.1201/9781003566496-33

Abstract

Accurate extraction of interconnect parasitics is vital for timing, signal integrity, power grid, and noise analyses in deep-submicron to millimeter-wave designs. This chapter surveys electromagnetic techniques that underpin state-of-the-art flows for interconnect impedance extraction. Analytical closed-form models provide rapid first-order estimates while being less accurate for dense, high-frequency layouts where distributed models of the interconnect and coupling effects are needed to more accurately characterize impedance characteristics. Differential-equation solvers, finite-difference, and finite-element methods (FEMs) mesh the entire volume, yielding sparse systems amenable to multigrid-preconditioned iterative solvers. Boundary/integral formulations such as boundary element method (BEM) and partial element equivalent circuit (PEEC) discretize only conductor surfaces, reducing unknowns yet producing dense matrices that demand hierarchical sparsification. The chapter contrasts these approaches in accuracy, computational complexity, domain handling, and frequency range and details hybrid workflows that leverage the strengths provided by each method. Variation-aware techniques, which include Monte Carlo (MC), polynomial-chaos expansions, stochastic model-order reduction (MOR), and floating random walks, capture process-induced geometry fluctuations. Lastly, machine-learning surrogates emerge as fast co-solvers, delivering hundred-to-thousand-fold speed-ups for self- and coupling capacitance, crosstalk, and RLC estimation while providing uncertainty estimates that are utilized to selectively fall back to physics-based engines. Together, the presented methods form a framework that balances complexity, accuracy, and computational cost when calculating parasitics needed for analysis during physical design and circuit verification.

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