Conference proceeding
1/4 W optical receiver and clock recovery circuit for Gb/s digital fiberoptic links
1996 IEEE MTT-S International Microwave Symposium Digest, v 2, pp 891-894 vol.2
1996
Abstract
Design and simulation of a low power consuming MMIC chip set is presented in this paper, which is used as an optical receiver and clock recovery circuit operating up to 1.25 Gb/s. This design is based on BTA24 Si BJT transistor array from Bipolarics. Major design innovations such as push-pull self-oscillating mixer and a push-push frequency doubler is used to provide a total power consumption of 247 mW in an area of only 700 /spl mu/m/spl times/700 /spl mu/m.
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Details
- Title
- 1/4 W optical receiver and clock recovery circuit for Gb/s digital fiberoptic links
- Creators
- A.S Daryoush - Drexel UniversityX ZhangJ.Y Lin
- Publication Details
- 1996 IEEE MTT-S International Microwave Symposium Digest, v 2, pp 891-894 vol.2
- Publisher
- IEEE
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:A1996BF95U00206
- Other Identifier
- 991019170477204721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Engineering, Electrical & Electronic