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A 0.45 pJ/bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators
Conference proceeding

A 0.45 pJ/bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators

Baris Taskin
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings
01 Jan 2022
DOI: https://doi.org/10.1109/ISCAS48785.2022.9937492

Abstract

Circuits Experimentation Oscillators Traveling waves
Conference Title: 2022 IEEE International Symposium on Circuits and Systems (ISCAS) Conference Start Date: 2022, May 27 Conference End Date: 2022, June 1 Conference Location: Austin, TX, USAIn this work, a die-to-die communication architecture with the integration of resonant clocking is presented. The novelty of the architecture are the rotary traveling wave oscillators, designed across the interposer of a 2. 5D multi-die system to provide a synchronous high frequency clock to all chiplets simultaneously. The transmitter and receiver interface circuits of the architecture benefit from the use of the low power, low skew, multiple phase clock signals across the chiplets. In experimentation, a channel length of 4 mm between transceivers is investigated over a 5 mm $\times 5$ mm silicon interposer. SPICE based simulations with post-layout, parasitic extracted models are performed. The proposed architecture demonstrates 20 Gb/s operation at 0.45 pJ/bit over a 4mm channel at a nominal 1 V supply voltage. The overall clock power of the proposed architecture is 56% lower than prior works at 20 Gb/s.

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Web of Science research areas
Engineering, Electrical & Electronic
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