Conference proceeding
A 900 MHz Charge Recovery Comparator With 40 fJ per Conversion
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), v 2018-, pp 1-5
01 Jan 2018
Abstract
The idea of recycling part of the charge used to drive a load is well understood in digital circuits, and falls under the umbrella term of charge recovery logic (CRL). By recovering part of the charge from the load, these circuits achieve lower energy consumption with respect to static CMOS. Recently, a comparator that uses the principles of charge recovery was presented, introducing these energy advantages to the world of mixed-signal circuits. The original design has a maximum operating frequency of 1kHz, and thus is limited to niche applications. In this work, an improved charge recovery comparator is introduced, operating at up to 900MHz. Post-layout simulations in 65nm technology show an energy consumption of 40 fJ per conversion, and an input offset voltage of 32mV
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Details
- Title
- A 900 MHz Charge Recovery Comparator With 40 fJ per Conversion
- Creators
- Leo Filippini - Drexel UniversityBaris Taskin - Drexel UniversityIEEE
- Publication Details
- 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), v 2018-, pp 1-5
- Series
- IEEE International Symposium on Circuits and Systems
- Publisher
- IEEE
- Number of pages
- 5
- Grant note
- CNS-1305350 / National Science Foundation; National Science Foundation (NSF)
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000451218701025
- Scopus ID
- 2-s2.0-85057091155
- Other Identifier
- 991019168073604721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Engineering, Electrical & Electronic