A Digital Neuromorphic Architecture for Unsupervised Shortest Path Computation on Real-World Graphs

Arghavan Mohammadhassani; Shadi Matinizadeh; L. M. Varshika; Anup Das

doi:10.1109/ISCAS56072.2025.11043988

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A Digital Neuromorphic Architecture for Unsupervised Shortest Path Computation on Real-World Graphs

Arghavan Mohammadhassani, Shadi Matinizadeh, L. M. Varshika and Anup Das

IEEE International Symposium on Circuits and Systems proceedings, pp 1-5

25 May 2025

DOI: https://doi.org/10.1109/ISCAS56072.2025.11043988

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Abstract

axonal plasticity

Delays

E-Prop

Field programmable gate arrays

FPGA

Graph analytics

Learning systems

Network-on-chip

network-on-chip (NoC)

Neural activity

neuromorphic

Neuromorphics

Scalability

Synapses

tile

Computer Architecture

Neurons

Graphs are popular tools for analyzing interconnected data entities. We propose SENTIENCE, a novel approach to computing the shortest path in a graph in an unsupervised manner drawing inspiration from the hippocampus. SENTIENCE uses laterally-connected neurons to represent nodes and synapses to represent edges. The strength of a synaptic connection is encoded as the axonal delay. When a neuron (source) is excited, a wavefront of neural activity is created that propagates through the graph via the connected nodes. SENTIENCE uses the Eligibility Propagation (E-Prop) algorithm to learn the sequence of wave movement through the shortest path in a graph, which can be obtained by identifying earliest firing (eligible) neighbors by tracing back in time from when the wavefront reaches a destination. We introduce a lightweight hardware design for the axonal plasticity and the E-Prop learning mechanism of SENTIENCE. We propose a tile-based architecture to address the scalability of SENTIENCE for real-world graphs with irregular data dependency. We evaluate SENTIENCE on a Versal VPK 180 FPGA and show that SENTIENCE consumes on average 10× less resources and 12× less power compared to a state-of-the-art.

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Title: A Digital Neuromorphic Architecture for Unsupervised Shortest Path Computation on Real-World Graphs
Creators: Arghavan Mohammadhassani - Drexel University
Shadi Matinizadeh - Drexel University
L. M. Varshika - Drexel University
Anup Das - Drexel University
Publication Details: IEEE International Symposium on Circuits and Systems proceedings, pp 1-5
Conference: 2025 IEEE International Symposium on Circuits and Systems (ISCAS) (London, United Kingdom, 25 May 2025–28 May 2025)
Publisher: IEEE
Resource Type: Conference proceeding
Language: English
Academic Unit: Electrical and Computer Engineering; Computer Science (Computing); College of Engineering
Scopus ID: 2-s2.0-105010594103
Other Identifier: 991022061054504721

A Digital Neuromorphic Architecture for Unsupervised Shortest Path Computation on Real-World Graphs

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