Conference proceeding
A High Level Synthesis Methodology for Dynamic Monitoring of FPGA ML Accelerators
2024 IEEE 42nd VLSI Test Symposium (VTS), pp 1-5
22 Apr 2024
Abstract
In this paper, we present concepts towards a HLS-driven dynamic monitoring and debugging framework. Traditionally, in-situ debugging and dynamic monitoring is accessible during the early design stages through costly co-simulation cycles and through invasive tools and interfaces. We propose a methodology where dynamic monitoring is embedded into the high level synthesis description of machine learning (ML) accelerators within the open source hls4ml tool. We discuss the usage of the framework for monitoring FIFO channel utilization, which is a critical structure utilized to implement streaming based ML accelerators on FPGAs.
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Details
- Title
- A High Level Synthesis Methodology for Dynamic Monitoring of FPGA ML Accelerators
- Creators
- Ryan F. Forelli - Lehigh UniversityRui Shi - Northwestern University,Department of Electrical and Computer EngineeringSeda Ogrenci - Northwestern University,Department of Electrical and Computer EngineeringJoshua Agar - Drexel University
- Publication Details
- 2024 IEEE 42nd VLSI Test Symposium (VTS), pp 1-5
- Publisher
- IEEE; NEW YORK
- Number of pages
- 5
- Grant note
- DoE ASRSP GCFA Grant: SP0062070 NSF POSE Phase II Grant: AWD00000665
This work was partially supported by DoE ASRSP GCFA Grant ID: SP0062070 and NSF POSE Phase II Grant AWD00000665.
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Mechanical Engineering and Mechanics
- Web of Science ID
- WOS:001239933000006
- Scopus ID
- 2-s2.0-85195238972
- Other Identifier
- 991021884693304721
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- Collaboration types
- Domestic collaboration
- Web of Science research areas
- Computer Science, Hardware & Architecture
- Computer Science, Theory & Methods
- Engineering, Electrical & Electronic