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A Power Side-Channel Attack on Flash ADC
Conference proceeding   Open access

A Power Side-Channel Attack on Flash ADC

Ziyi Chen and Ioannis Savidis
2023 IEEE International Symposium on Circuits and Systems (ISCAS), v 2023-, pp 1-5
21 May 2023
url
https://doi.org/10.1109/ISCAS46773.2023.10181331View
Published, Version of Record (VoR)Maybe Open Access (Publisher Bronze) Open

Abstract

ADC Codes power side-channel Quantization (signal) Resistors Security side-channel attack Side-channel attacks Thermometers Voltage
In this paper, a monotonic power side-channel attack (PSA) is proposed to analyze the security vulnerabilities of flash analog-to-digital converters (ADC), where the digital output of a flash ADC is determined by characterizing the monotonic relationship between the traces of the power consumed and the applied input signals. A novel technique that leverages clock phase division is proposed to secure the power side channel information of a 4-bit flash ADC. The proposed technique adds randomness to decorrelate the input signal from the given power trace as the execution phase of each comparator depends on a thermometer code computed from the previous seven clock cycles. The monotonic PSA is executed on both a secured and unsecured ADC, with results indicating 1.9 bits of information leakage from an unprotected ADC and no data leakage from a protected ADC as the bit-wise accuracy is approximately 50% when secured. The monotonic PSA is more effective at attacking a flash ADC architecture than either a convolutional neural network based PSA or a correlation template PSA. The secured ADC core occupies approximately 2% more area than a non-secure ADC in a 65 nm process, and provides a sampling frequency of up to 500 MHz at a supply voltage of 1.2 V.

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Computer Science, Artificial Intelligence
Computer Science, Information Systems
Engineering, Electrical & Electronic
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