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A Quasi-Analytic Behavioral Model for the Single-electron Transistor for Hybrid MOS/SET Circuit Simulation
Conference proceeding

A Quasi-Analytic Behavioral Model for the Single-electron Transistor for Hybrid MOS/SET Circuit Simulation

Francisco Castro, Ioannis Savidis and Arturo Sarmiento
2018 IEEE 13th Nanotechnology Materials and Devices Conference (NMDC)
Oct 2018

Abstract

Analytical models Conferences Integrated circuit modeling Inverters Logic gates Mathematical model Nanotechnology
A methodology to incorporate single-electron transistors (SET) into the IC design flow is introduced in this paper. A SET model is developed that is defined as a VERILOG-A module that can be used for SPICE-like simulation of hybrid circuits containing SET and MOS transistors. The SET model is formulated in a semi-symbolic form, which provides insight and intuition on the functionality of the device. The model was verified on a SET-only and hybrid (SET and MOS transistors) implementation of an inverter. The proposed model is compared with a verified analytical model that applies a master equation, which results in errors of approximately 1.6% for a SET-only inverter and 1.3% for a hybrid inverter.

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