Conference proceeding
A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop
Proceedings of the 2021 on Great Lakes Symposium on VLSI
22 Jun 2021
Abstract
This paper purposes a Reinforcement Learning solution for peak current reduction by clock skew engineering. The reinforcement learning agent learns how to adjust each register's clock arrival time to maximize the clock arrival's distribution. The use of reinforcement learning allows us to explore optimization opportunities in clock tree synthesis beyond the heuristic algorithms used in modern EDA tools. Our experimental results support this claim as we report over 35% drop in peak current and major reduction in IR drop (from package to transistor) in the selected benchmarks. The agent explores despite creating timing violations and receives a large negative reward for its action. The agent, however, can receive a bonus reward in the future if the timing violation was fixed later by adjusting the clock arrival time of other registers, resulting in a broader spread in clock arrival distribution.
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9 citations in Scopus
Details
- Title
- A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop
- Creators
- Sayed Aresh Beheshti-Shirazi - George Mason UniversityAshkan Vakil - George Mason UniversitySai Manoj - George Mason UniversityIoannis Savidis - Drexel UniversityHouman Homayoun - University of California, DavisAvesta Sasan - George Mason University
- Publication Details
- Proceedings of the 2021 on Great Lakes Symposium on VLSI
- Publisher
- ACM
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Scopus ID
- 2-s2.0-85109215052
- Other Identifier
- 991021811637904721