Conference proceeding
A charge recovery logic system bus
2017 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)
27 Jun 2017
Abstract
Modern VLSI systems are limited by power constraints, and many solutions exists to reduce power consumption. In static CMOS energy is dissipated by the pull-up and pull-down networks during low-to-high and high-to-low transitions, respectively. The charge is moved from the power source to the load capacitance, then discharged to ground. Charge recovery logic (CRL) saves energy by recovering, or recycling, this charge. While discrete-time filters and adders have been built in charge recovery logic, tristate gates, registers, and buses have seen moderate research. This work shows how a charge recovery logic bus can be built, and how the CRL bus can be accessed to support read and write operations. In addition, a novel CRL register is proposed as a representative memory device transacting read and write operations through the CRL bus.
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1 citations in Scopus
Details
- Title
- A charge recovery logic system bus
- Creators
- Leo Filippini - Drexel UniversityBaris Taskin - Drexel UniversityIEEE
- Publication Details
- 2017 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)
- Publisher
- IEEE
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000426908000005
- Scopus ID
- 2-s2.0-85027410800
- Other Identifier
- 991019203358604721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Automation & Control Systems
- Engineering, Electrical & Electronic