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A high power circuit model for the gate turn off thyristor
Conference proceeding

A high power circuit model for the gate turn off thyristor

C.L Tsay, R Fischl, J Schwartzenberg, H Kan and J Barrow
21st Annual IEEE Conference on Power Electronics Specialists, pp 390-397
1990

Abstract

Circuit simulation Circuit synthesis Computational modeling Computer simulation Electric resistance P-n junctions Power electronics Resistors SPICE Thyristors
The authors present GTO (gate turn off thyristor) model which simulates both the static negative differential resistance characteristics and the dynamic switching characteristics. The model consists of parallel connection of two-transistor, three-resistor (2T-3R) circuits which make it compatible with the SPICE program. An experimental validation test shows that the accuracy of the model can be improved by increasing the number of 2T-3R cells.< >

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