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Advanced timing of level-sensitive sequential circuits
Conference proceeding

Advanced timing of level-sensitive sequential circuits

B Taskin, I.S Kourtev and IEEE
Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004, pp 603-606
2004
DOI: https://doi.org/10.1109/ICECS.2004.1399753

Abstract

Circuit analysis Circuit topology Clocks Frequency synchronization Minimization Processor scheduling Propagation delay Registers Sequential circuits Timing
The paper addresses the advanced timing analysis of multiphase level-sensitive synchronous circuits under clock skew scheduling (Kourtev, I.S. and Friedman, E.G., "Optimization Through Clock Skew Scheduling", Kluwer Academic Publishers, 2000). The timing analysis framework previously offered for a single-phase clocking scheme (Taskin, B. and Kourtev, I.S., Proc. 15th IEEE Int. ASIC/SOC Conf. p.358-62, 2002) is enhanced to accommodate a multiphase clocking scheme. In particular, the timing analysis framework is used to formulate the clock period minimization problem of multiphase level-sensitive circuits. The modified big M method of Taskin and Kourtev is used to linearize the formulation of the clock period minimization problem and experiments are performed on the ISCAS'89 benchmark circuits. In single-phase level-sensitive circuits, up to 63% improvements over conventional zero clock skew, edge-triggered circuits are achieved through the simultaneous application of non-zero clock skew scheduling and time borrowing. Comparable improvements of up to 62% are achieved for the same circuit topologies under a multiphase clocking scheme.

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Web of Science research areas
Computer Science, Hardware & Architecture
Engineering, Electrical & Electronic
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