Conference proceeding
Automatic Circuit Topology Generation on a Reconfigurable Analog Array
IEEE International Symposium on Circuits and Systems proceedings, pp 1007-1011
24 May 2026
Abstract
In this paper, a framework is proposed to automatically generate circuit topologies on a Field-Programmable Analog Array (FPAA) based on user-provided specifications. A Monte Carlo Tree Search (MCTS) algorithm is utilized to optimize device selection, transistor pair topology selection, and routing. During the device selection stage, the algorithm determines whether to expand the number of devices used for implementation of a circuit. In the topology selection stage, the structured configuration of the selected devices is finalized, while in the routing selection stage the connections between devices are established. A Bayesian optimization algorithm is executed to determine the transistor sizes of the circuit topologies generated by the MCTS algorithm, which optimizes the performance of each generated topology with feedback provided through SPICE simulation. Experimental results demonstrate that execution of the proposed flow successfully results in the creation of different circuit topologies of an operational amplifier (op amp) that meet the specifications and constraints provided by the user. After 23 executed iterations, the proposed MCTS algorithm generates circuits that achieve a 26% higher performance score than circuits generated with a random tree search (RTS) algorithm.
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Details
- Title
- Automatic Circuit Topology Generation on a Reconfigurable Analog Array
- Creators
- Ziyi Chen - Drexel UniversityIoannis Savidis - Drexel University
- Publication Details
- IEEE International Symposium on Circuits and Systems proceedings, pp 1007-1011
- Publisher
- IEEE
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Other Identifier
- 991022193498104721