Conference proceeding
Charge Recovery Implementation of an Analog Comparator: Initial Results
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings, pp 1505-1508
01 Jan 2017
Abstract
Conference Title: 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS) Conference Start Date: 2017, Aug. 6 Conference End Date: 2017, Aug. 9 Conference Location: Boston, MA, USA This work introduces a charge recovery comparator circuit for low-power, low-frequency applications. For the first time, the principles of charge recovery logic, or adiabatic logic, are applied to an analog circuit. The comparator is designed and simulated in a 180 nm technology and compared to state of the art solutions. Post-extraction simulations show that the proposed comparator consumes only 46 fJ per conversion in the nominal PVT corner, while having a total area of 45 μm2. The proposed comparator consumes up to 70 % less power than a state of the art dynamic latch comparator.
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Details
- Title
- Charge Recovery Implementation of an Analog Comparator: Initial Results
- Creators
- Leo Filippini - Drexel University, Electrical and Computer EngineeringLunal Khuon - Drexel UniversityBaris Taskin - Drexel University, Electrical and Computer Engineering
- Publication Details
- The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings, pp 1505-1508
- Series
- Midwest Symposium on Circuits and Systems Conference Proceedings
- Publisher
- The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
- Number of pages
- 4
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000424694700376
- Scopus ID
- 2-s2.0-85034054318
- Other Identifier
- 991019170347204721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Engineering, Electrical & Electronic
- Telecommunications