Conference proceeding
Circuit-GNN: A Graph Neural Network for Transistor-level Modeling of Analog Circuit Hierarchies
2023 IEEE International Symposium on Circuits and Systems (ISCAS), v 2023-, pp 1-5
21 May 2023
Featured in Collection : UN Sustainable Development Goals @ Drexel
Abstract
Recently, graph neural networks (GNNs) have been applied to various circuit applications, where circuit topology is leveraged in the learning of the models. However, the aggregation of GNN models has not accounted for circuit hierarchies. In addition, the generalization of GNNs to distinguish between different circuit topologies is not currently provided, which raises the question of whether one GNN is sufficient to simultaneously model differing circuit graphs. In this work, a graph representation is proposed, based on a given circuit netlist, to model analog circuits at the transistor level. Additional categorical features are included to address the ambiguity in modeling the connections of the terminals of a given transistor. Edge-conditioned convolution (ECC) is utilized, where weight matrices conditioned on the edge attributes are trained in the local neighborhood of a given node. A relational graph is constructed to model groupings of devices for each level of the hierarchy provided by the designer. Each adjacency matrix of the relational graph is processed by a graph isomorphism network (GIN) layer, described as a Circuit-GIN layer, to update the node embeddings. The model consisting of an ECC layer and two Circuit-GIN layers, described as a Circuit-GNN, is trained on data from four op-amp topologies to predict four performance parameters. Results indicate that the ECC-based model outperforms a GCN-based model in the prediction of all of the performance parameters, which results from the additional edge information learned by the ECC layer. With the addition of Circuit-GIN layers, the Circuit-GNN outperforms the ECC-only model by up to 16.7% in \boldsymbol{R}^{\mathbf{2}} score. Therefore, aggregation of node embeddings based on device groupings brings additional benefit to guide the GNNs in modeling the performance of analog ICs. The work also validates the expressive power of the proposed GNN model, which generates embeddings that distinguish between different circuit graphs. The generalization of GNNs renders feasible the simultaneous learning from different analog topologies.
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Details
- Title
- Circuit-GNN: A Graph Neural Network for Transistor-level Modeling of Analog Circuit Hierarchies
- Creators
- Zhengfeng Wu - Drexel UniversityIoannis Savidis - Drexel University
- Publication Details
- 2023 IEEE International Symposium on Circuits and Systems (ISCAS), v 2023-, pp 1-5
- Publisher
- IEEE
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:001038214601034
- Scopus ID
- 2-s2.0-85167661829
- Other Identifier
- 991021057566604721
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InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Computer Science, Artificial Intelligence
- Computer Science, Information Systems
- Engineering, Electrical & Electronic