Conference proceeding
Clock Distribution Networks for 3-D Integrated Circuits
PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE, pp 651-654
01 Jan 2008
Featured in Collection : UN Sustainable Development Goals @ Drexel
Abstract
Three-dimensional (3-D) integration is an important technology that addresses fundamental limitations of on-chip interconnects. Several design issues related to 3-D circuits, such as multi-plane synchronization, however, need to be addressed. A comparison of three 3-D clock distribution network topologies is presented in this paper. Experimental results of a 3-D test circuit manufactured by the MIT Lincoln Laboratories are also described. Successful operation of the 3-D test circuit at 1.4 GHz is demonstrated. Clock skew and power dissipation measurements for the different clock topologies are also provided.
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Details
- Title
- Clock Distribution Networks for 3-D Integrated Circuits
- Creators
- Vasilis F. Pavlidis - Univ Rochester, Dept Elect & Comp Engn, Rochester, NY 14627 USAIoannis Savidis - University of RochesterEby G. Friedman - University of RochesterIEEE
- Publication Details
- PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE, pp 651-654
- Series
- IEEE Custom Integrated Circuits Conference
- Publisher
- IEEE
- Number of pages
- 4
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000262643900145
- Scopus ID
- 2-s2.0-57849119713
- Other Identifier
- 991019186639904721
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- Web of Science research areas
- Engineering, Electrical & Electronic