Conference proceeding
Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering
2012 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), pp 691-697
01 Jan 2012
Abstract
A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path in the design. This is the first work known in literature that encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. Experimental results show that with gated local tree and activity driven register clustering, the switching capacitance on the mesh network can be reduced by 22% with limited skew degradation. The proposed method has two synthesis modes as low power mode and high performance mode to serve different design purposes.
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Details
- Title
- Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering
- Creators
- Jianchao Lu - SynopsysXiaomi Mao - OracleBaris Taskin - Drexel UniversityIEEE
- Publication Details
- 2012 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), pp 691-697
- Series
- ICCAD-IEEE ACM International Conference on Computer-Aided Design
- Publisher
- IEEE
- Number of pages
- 7
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000317001300113
- Scopus ID
- 2-s2.0-84872293281
- Other Identifier
- 991019173689704721
InCites Highlights
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- Collaboration types
- Industry collaboration
- Domestic collaboration
- Web of Science research areas
- Computer Science, Software Engineering
- Engineering, Electrical & Electronic