Conference proceeding
Clock Tree Synthesis with XOR Gates for Polarity Assignment
IEEE ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2010), pp 17-22
01 Jan 2010
Abstract
A novel clock tree synthesis (CTS) method is proposed that improves the reliability of an integrated circuit system through reducing the peak current on the power/ground rails drawn by the clock tree buffers. The proposed CTS method entails the integration of XOR gates at one level of the clock tree to enable polarity assignment for peak current reduction. Unlike previous polarity assignment methods, the skew of the generated clock tree with XORs is preserved as the physical layout of the clock tree is preserved during the polarity assignment process. Furthermore, the proposed clock tree permits the implementation of most of the previous polarity assignment methods through configurability of the control input of the XOR gates. Experimental results show that the peak current on the power/ground rails of the clock tree is reduced by an average of 55.2% without any degradation in the original clock skew.
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Details
- Title
- Clock Tree Synthesis with XOR Gates for Polarity Assignment
- Creators
- Jianchao Lu - Drexel UniversityBaris Taskin - Drexel UniversityIEEE Comp Soc
- Publication Details
- IEEE ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2010), pp 17-22
- Series
- IEEE Computer Society Annual Symposium on VLSI
- Publisher
- IEEE
- Number of pages
- 6
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000407131800007
- Scopus ID
- 2-s2.0-77957893056
- Other Identifier
- 991019169418804721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Computer Science, Hardware & Architecture
- Engineering, Electrical & Electronic