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Conference proceeding
Clock distribution models of 3-D integrated systems
2011 IEEE International Symposium of Circuits and Systems (ISCAS), pp 2225-2228
May 2011
Abstract
Clock distribution topologies in a three-tier 3-D integrated circuit are explored. Models of three different clock topologies are applied to determine the root to leaf delay. The models incorporate the impedance of the 3-D via between planes based on closed-form expressions of the resistance, inductance, and capacitance of a through silicon via (TSV). The resulting modeled delays are compared to experimental data. Good agreement between simulation and experimental data is achieved.
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Details
- Title
- Clock distribution models of 3-D integrated systems
- Creators
- Ioannis Savidis - University of RochesterVasilis Pavlidis - Dept. of Electr. & Comput. Eng., Univ. of Rochester, Rochester, NY, USAEby G Friedman - Dept. of Electr. & Comput. Eng., Univ. of Rochester, Rochester, NY, USAIEEE
- Publication Details
- 2011 IEEE International Symposium of Circuits and Systems (ISCAS), pp 2225-2228
- Publisher
- IEEE
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000297265302138
- Scopus ID
- 2-s2.0-79960865002
- Other Identifier
- 991019186646404721
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- Web of Science research areas
- Engineering, Electrical & Electronic