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Corruptibility Profile of Logic Locked Circuits for SAT Attacks with Execution Time Budgets
Conference proceeding

Corruptibility Profile of Logic Locked Circuits for SAT Attacks with Execution Time Budgets

Saran Phatharodom and Ioannis Savidis
2022 IEEE 15th Dallas Circuit And System Conference (DCAS), pp 1-5
17 Jun 2022

Abstract

Circuits and systems Closed-form solutions Conferences Current measurement Measurement Probabilistic logic Probability distribution
In addition to attack resilience, the corruptibility of the outputs is another important metric evaluating the security of a logic locked circuit. The current practice is to evaluate and report the corruptibility for the scenario where an attacker randomly selects a key pattern without first performing any attack to narrow the key space. However, the measured corruptibility potentially changes rapidly after some initial effort by the attacker. Consequently, a probabilistic framework is proposed to characterize and report the expected output corruptibility as a function of the set constraints, specifically the budget b (number of attack iterations), in computational effort for a satisfiability (SAT) attack. Closed-form expressions of the mean and the probability distribution of the output corruptibility produced by two logic locking techniques (SARLock and TTLock) are derived and compared. The mean of the output corruptibility for SARLock is \displaystyle \frac{(\rho-1-b)}{(\rho-b)\rho} and that of TTLock is \displaystyle \frac{2(\rho-1-b)}{\rho^{2}}, where \rho=2^{\text{keysize}}. The results indicate that TTLock outperforms SARLock when the SAT attack iteration budget is less than the break even point of \rho/2, while SARLock provides greater output corruptibility above the break even point.

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Computer Science, Interdisciplinary Applications
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