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Criticality-aware scrubbing mechanism for SRAM-based FPGAs
Conference proceeding

Criticality-aware scrubbing mechanism for SRAM-based FPGAs

Rui Santos, Shyamsundar Venkataraman, Anup Das and Akash Kumar
2014 24th International Conference on Field Programmable Logic and Applications (FPL), pp 1-8
Sep 2014
DOI: https://doi.org/10.1109/FPL.2014.6927476

Abstract

Equations Fault tolerance Fault tolerant systems Field programmable gate arrays Hardware Schedules
Scrubbing has been considered as an effective mechanism to provide fault-tolerance in Static-RAM (SRAM)-based Field Programmable Gate Arrays (FPGAs). However, the current scrubbing techniques execute without considering the criticality and timing of the user tasks implemented in the FPGA. They often do not execute the scrubbing process in the right instant, which minimizes the probability of each task being executed without transient faults. Moreover, these current solutions are not adapted to the tasks' fault-tolerance requirements, since they may not properly protect the most critical tasks in the system. However, if they do it, they waste resources with the less critical tasks. In this paper, a new scrubbing mechanism is proposed. This new approach adapts the scrubbing mechanism to the tasks' execution, by a proper scheduling and according to their criticality. A proposed heuristic finds a feasible scrubbing schedule for each hardware task. Firstly, the minimum scrubbing periods are computed according to the criticality of each implemented hardware task. Secondly, a proper scrubbing schedule following the EDL (Earliest Deadline as Late as possible) algorithm is found, maximizing the reliability of the system. The experimental results show up to 79% improvements on the system reliability, achieved without wasting scrubbing resources.

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