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Design Methodologies for Reliable and Energy-efficient PCM Systems
Conference proceeding   Open access

Design Methodologies for Reliable and Energy-efficient PCM Systems

Shihao Song and Anup Das
2020 11th International Green and Sustainable Computing Workshops (IGSC), pp 1-3
19 Oct 2020
DOI: https://doi.org/10.1109/IGSC51522.2020.9291024
url
https://arxiv.org/abs/2011.13959View
Submitted Open Open Access (License Unspecified)

Abstract

bitline parasitic design methodologies DRAM DRAM chips endurance energy energy consumption energy penalties energy-efficient PCM Hardware high operating voltages high-density synaptic storage higher latency hybrid memory Integrated circuit reliability low access Memory management multilevel property NBTI neuromorphic computing neuromorphic systems non-volatile memory (NVM) Nonvolatile memory nonvolatile memory technology PCM cells PCM system performance phase change materials phase change memories phase change memory (PCM) phase-change memory Random access memory random-access storage Reliability reliable operations storage class memory storage management tiered memory
Phase-change memory (PCM) is a scalable and low latency non-volatile memory (NVM) technology that has been proposed to serve as storage class memory (SCM), providing low access latency similar to DRAM and often approaching or exceeding the capacity of SSD. The multilevel property of PCM also enables its adoption in neuromorphic systems to build high-density synaptic storage. We investigate and describe two significant bottlenecks of a PCM system. First, writing to PCM cells incurs significantly higher latency and energy penalties than reading its content. Second, high operating voltages of PCM impacts its reliable operations. In this work, we propose methodologies to tackle the bottlenecks, improving performance, reliability, energy consumption, and sustainability for a PCM system.

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