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Design Technology Co-Optimization for Neuromorphic Computing
Conference proceeding   Open access

Design Technology Co-Optimization for Neuromorphic Computing

Ankita Paul, Shihao Song and Anup Das
2021 12th International Green and Sustainable Computing Conference (IGSC), pp 1-6
18 Oct 2021
DOI: https://doi.org/10.1109/IGSC54211.2021.9651556
url
http://arxiv.org/abs/2110.08131View
SubmittedOpen Access (License Unspecified),  Open

Abstract

Computational modeling Hardware Machine learning Neuromorphic engineering Nonvolatile memory Resistance Voltage
We present a design-technology tradeoff analysis in implementing machine-learning inference on the processing cores of a Non-Volatile Memory (NVM)-based many-core neuromorphic hardware. Through detailed circuit-level simulations for scaled process technology nodes, we show the negative impact of design scaling on read endurance of NVMs, which directly impacts their inference lifetime. At a finer granularity, the inference lifetime of a core depends on 1) the resistance state of synaptic weights programmed on the core (design) and 2) the voltage variation inside the core that is introduced by the parasitic components on current paths (technology). We show that such design and technology characteristics can be incorporated in a design flow to significantly improve the inference lifetime.

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