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Design of a Tunable Astrocyte Neuromorphic Circuitry with Adaptable Fault Tolerance
Conference proceeding

Design of a Tunable Astrocyte Neuromorphic Circuitry with Adaptable Fault Tolerance

M. L. Varshika, Sarah Johari, Jayanth Dubey and Anup Das
Conference proceedings : Midwest Symposium on Circuits and Systems, pp 904-908
2023
DOI: https://doi.org/10.1109/MWSCAS57524.2023.10405978

Abstract

Astrocyte Bipartite Synapse Neu-romorphic Circuitry Spiking Neural Network (SNN) Tripartite Synapse
Astrocytes are the star-shaped glial cells in a mammalian brain that facilitate self-repair by restoring the spike firing frequency of failed neurons. We design an astrocyte neuromorphic circuitry in 90nm CMOS. Our astrocyte parameters can be tuned to achieve different degrees of fault tolerance in the design. First, we implement a Leaky-Integrate-and-Fire (LIF) neuron with analog synapses enclosed with an astrocyte circuitry that provides a closed-loop retrograde feedback signal to the neuron. This feedback is responsible for reinstating the activity level at a faulty synaptic site. Next, we propose two adaptable fault tolerance approaches for designing a neuromorphic core - a partitioned design with multiple astrocytes and a single-astrocyte design with adjustable fault tolerance. Through extensive circuit-level simulations, we show the adaptive fault-tolerant behavior of our proposed design to randomly-injected faults.

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