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Dynamic idle core management and leakage current reuse in MPSoC platforms
Conference proceeding

Dynamic idle core management and leakage current reuse in MPSoC platforms

M D Hossain and Ioannis Savidis
Proceedings of the ACM/IEEE International Symposium on low power electronics and design
10 Aug 2020
DOI: https://doi.org/10.1145/3370748.3406558

Abstract

In this paper, algorithmic and circuit techniques are proposed for dynamic power management that allows for the reuse of the leakage current of idle circuit blocks and cores in a multiprocessor system-on-chip platform. First, a novel scheduling algorithm, longest idle time - leakage reuse (LIT-LR) , is proposed for energy efficient reuse of leakage current, which generates a supply voltage of 340 mV with less than ±3% variation across the tt, ff, and ss process corners. The LIT-LR algorithm reduces the energy consumption of the leakage control blocks and the peak power consumption by, respectively, 25% and 7.4% as compared to random assignment of idle cores for leakage reuse. Second, a novel usage ranking based algorithm, longest idle time - simultaneous leakage reuse and power gating (LIT-LRPG) , is proposed for simultaneous implementation of power gating and leakage reuse. Applying power gating with leakage reuse reduces the total energy consumption of the MPSoC by 50.2%, 14.4%, and 5.7% as compared to, respectively, a baseline topology that includes neither leakage reuse or power gating, only includes power gating, and only includes leakage reuse.

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