Conference proceeding
Edge-weighted Graph Neural Networks for Post-placement Interconnect Capacitance Estimation of Analog Circuits
2024 IEEE International Symposium on Circuits and Systems (ISCAS), pp 1-5
19 May 2024
Abstract
With technology scaling, interconnect impedance becomes a dominant factor that affects the performance of integrated circuits. Estimating the interconnect impedance of analog circuits at early design stages has been a persistent challenge, primarily due to the lack of detailed layout information. Even with accurate parasitic extraction after routing, many iterations of modifications to the design are required to compensate for the effects of interconnect impedance. To address this challenge, a novel approach is proposed in this work that leverages graph neural networks (GNNs) for the estimation of the interconnect capacitance of an analog circuit at both the schematic and post-placement stages of the design flow. A device-level circuit is represented as a heterogeneous graph, where two node types are utilized, one representing transistors and the other representing nets. The GNN model, specifically, the relational GraphSAGE network, is applied to update the embeddings of net nodes, which are then used to predict the lumped capacitance of a net. To allow the model to learn the spatial relationships between devices after placement, the pairwise Manhattan distances between devices are utilized as edge weights during the aggregation of node embeddings. A dataset of ten analog circuits is utilized to evaluate the proposed model. The developed GNN model for post-placement prediction of capacitance that utilizes pairwise Manhattan distances results in an R 2 score of 0.73 and a mean absolute error of 0.26 fF, outperforming both the schematic-level prediction model and the post-placement prediction model that directly utilizes device coordinates as features. Results confirm that the proposed model effectively estimates the interconnect capacitance of analog circuits at early design stages while requiring a small dataset for training.
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Details
- Title
- Edge-weighted Graph Neural Networks for Post-placement Interconnect Capacitance Estimation of Analog Circuits
- Creators
- Zhengfeng Wu - Drexel UniversityIoannis Savidis - Drexel University
- Publication Details
- 2024 IEEE International Symposium on Circuits and Systems (ISCAS), pp 1-5
- Publisher
- IEEE; NEW YORK
- Number of pages
- 5
- Grant note
- Office of Naval Research (10.13039/100000006) National Science Foundation (10.13039/100000001)
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:001268541104052
- Scopus ID
- 2-s2.0-85198556936
- Other Identifier
- 991021893600204721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Computer Science, Interdisciplinary Applications
- Engineering, Electrical & Electronic