Conference proceeding
Efficient test generation for built-in self-test boundary-scan template
Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's, pp 277-284
1991
Abstract
An analysis and design of a pseudorandom pattern generator, (PRPG), based on a linear recurrence, for built-in self-test (BIST) boundary scan design is presented. The authors present for the case when r>or=s, a design of an s-stage PRPG capable of producing 2/sup s/-1 distinct r-bit patterns within 2/sup s/-1 clock pulses independent of the hardware realization of the PRPG. For the case when r<s, the expected number N(T) of PRPG clock pulses required for generating T<or=2/sup r/ distinct r-bit patterns and the expected number T(N) of distinct patterns given a number N of clock pulses were presented. The proposed theoretical average N(T) was shown to be close to the experimental average values N/sub ex/(T). Hence, the value N(T) or T(N) can be used as a benchmark for evaluating the efficiency of a BIST boundary scan test generation.< >
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Details
- Title
- Efficient test generation for built-in self-test boundary-scan template
- Creators
- P Nagvajara - Drexel UniversityM.G Karpovsky - Boston UniversityL.B Levitin - Boston University
- Publication Details
- Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's, pp 277-284
- Conference
- 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's
- Publisher
- IEEE
- Number of pages
- 1
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Scopus ID
- 2-s2.0-85069716399
- Other Identifier
- 991019182662404721