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ElasticCore: Enabling dynamic heterogeneity with joint core and voltage/frequency scaling
Conference proceeding

ElasticCore: Enabling dynamic heterogeneity with joint core and voltage/frequency scaling

Mohammad Khavari Tavana, Mohammad Hossein Hajkazemi, Divya Pathak, Ioannis Savidis, Houman Homayoun and IEEE
2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), v 2015-, pp 1-6
Jun 2015

Abstract

Bandwidth Benchmark testing Computer architecture DVFS Energy efficiency regression model Regulators Sensitivity Voltage control voltage regulator
Heterogeneous architectures have emerged as a promising solution to enhance energy-efficiency by allowing each application to run on a core that matches resource needs more closely than a one-size-fits-all core. In this paper, an ElasticCore platform is described where core resources along with the operating voltage and frequency settings are scaled to match the application behavior at run-time. Furthermore, a linear regression model for power and performance prediction is used to guide the scaling of the core size and the operating voltage and frequency to maximize efficiency. Circuit considerations that further optimize the power efficiency of ElasticCore are also considered. Specifically, the efficiency of both off-chip and on-chip voltage regulators is analyzed for the heterogeneous architecture where the required load current changes dynamically at run-time. A distributed on-chip voltage regulator topology is proposed to accommodate the heterogeneous nature of the ElasticCore. The results indicate that ElasticCore on average achieves close to a 96% efficiency as compared to an architecture implementing the Oracle predictor where the application behavior is perfectly matched at run-time. Moreover, the proposed architecture is 30% more energy-efficient as compared to the BigLitte architecture.

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Collaboration types
Domestic collaboration
Web of Science research areas
Engineering, Electrical & Electronic
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