Conference proceeding
Electrical modeling and characterization of 3-D vias
PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, pp 784-787
01 Jan 2008
Abstract
Electrical characterization of the resistance, capacitance, and inductance of inter-plane 3-D vias is presented in this paper. Both capacitive and inductive coupling between multiple 3-D vias is described as a function of the separation distance and plane location. The effects of placing a third shield via between two signal vias is investigated as a means to limit the capacitive coupling. The location of the return path is examined to determine the best placement of a 3-D via to reduce the overall loop inductance. Based on the extracted resistance, capacitance, and inductance, the L/R time constant is shown to be much larger than the RC time constant, demonstrating that the 3-D via structure investigated in this paper is inductively limited rather than capacitively limited.
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Details
- Title
- Electrical modeling and characterization of 3-D vias
- Creators
- Ioannis Savidis - University of RochesterEby G. Friedman - University of RochesterIEEE
- Publication Details
- PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, pp 784-787
- Series
- IEEE International Symposium on Circuits and Systems
- Publisher
- IEEE
- Number of pages
- 4
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000258532100200
- Scopus ID
- 2-s2.0-51749103545
- Other Identifier
- 991019186783104721
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- Web of Science research areas
- Computer Science, Hardware & Architecture
- Computer Science, Information Systems
- Engineering, Electrical & Electronic
- Physics, Applied
- Telecommunications