Conference proceeding
Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling
2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp 1-3
07 Nov 2021
Abstract
Moore's Law (Fig.1) has worked like a self-fulfilled prophecy for over 50 years since Gordon Moore's 1965 prediction of integrated circuits. It sets the pace of the semiconductor industry, including lithography tools, device and material technologies, simulation software, testing equipment, and etc., along an exponential growth line, i.e., transistor density to double every \sim 18 months. The world has seen a transformational change, as exemplified by massive computing and communication capability in data centers, wired/wireless networks, smartphones, wearables, and IoTs, and continued growth in AI, robotics, unmanned vehicles, VR, and many more. Fig.2 is the performance trend of supercomputers, a precursor of future computers, now near the exaFlops line. The most powerful machine has an energy efficiency of 68pJ/Flop. How much can be squeezed?
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Details
- Title
- Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling
- Creators
- Shenggao Li - TSMCChien-Chun Tsai - TSMCEric Soenen - TSMCFrank J C Lee - TSMCCheng-Hsiang Hsieh - TSMCIEEE
- Publication Details
- 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp 1-3
- Publisher
- IEEE
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Digital Media
- Web of Science ID
- WOS:000768220800053
- Scopus ID
- 2-s2.0-85123990907
- Other Identifier
- 991020594699004721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Engineering, Electrical & Electronic