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Evaluation of the static performance of a simulation-stimulation interface for power hardware in the loop
Conference proceeding

Evaluation of the static performance of a simulation-stimulation interface for power hardware in the loop

S Ayasun, R Fischl, T Chmielewski, S Vallieu, K Miu and C Nwankpa
2003 IEEE Bologna Power Tech Conference Proceedings, v 3, 1004
2003
DOI: https://doi.org/10.1109/PTC.2003.1304513

Abstract

Delay effects Hardware Hybrid power systems Power engineering and energy Power system measurements Power system modeling Power system simulation Test facilities Time domain analysis USA Councils
This work gives an evaluation framework of the static performance of a simulation-stimulation interface (SSI) for power hardware in the loop (PHIL) applications. The PHIL system is a hybrid system consisting of hardware-under-test (HUT) connected to a virtual rest of the power system (VROPS) via a simulation-stimulation interface (SSI). The SSI maps the discrete time input/output signals of the VROPS to the continuous time power input/output signals of the HUT. Ideally, the performance of the PHIL should be the same as the actual power system consisting of the HUT connected to the rest of the system hardware. The evaluation of the PHIL performance is made in terms of its electric power matching capability. Since the SSI is the key component affecting the power matching, this paper evaluates the effect of the SSI parameters on the static performance of PHIL, specifically, the power system loadability/maximum power transfer. The results are illustrated using P-Q curves of simple 2-bus 1/spl phi/ system consisting of a generator, line and RL load. An experimental system was used to generate the baseline data for the simulation that was performed using Simulink. The study concentrated on the effect of time delay encountered in the SSI and VROPS processing on the maximum power transfer (i.e., P-Q curves) of the PHIL relative to that of the experimental system. The results show the decrease in maximum power transfer capability as the time delay increases to 1 msec.

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