Conference proceeding
Exploiting Useful Skew in Gated Low Voltage Clock Trees
2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), pp.2595-2598
IEEE International Symposium on Circuits and Systems
01 Jan 2016
Abstract
Low swing/voltage clocking is a well-studied approach to reduce dynamic power consumption in clock networks. It is, however, challenging to maintain the same performance at scaled clock voltages due to timing degradation in the Enable paths that are required for clock gating, another highly popular method to reduce dynamic power. A useful skew methodology is proposed in this paper to increase the timing slack of the Enable paths when the clock network is operating at a lower swing voltage. The skew schedule is determined via linear programming. The methodology is evaluated on five largest IS-CAS' 89 benchmark circuits. The results demonstrate an average 47% increase in the timing slack of the Enable path, thereby facilitating low swing operation without degrading performance.
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Details
- Title
- Exploiting Useful Skew in Gated Low Voltage Clock Trees
- Creators
- Weicheng Liu - SUNY Stony Brook, Dept Elect & Comp Engn, Stony Brook, NY 11794 USAEmre Salman - SUNY Stony Brook, Dept Elect & Comp Engn, Stony Brook, NY 11794 USACan Sitik - Drexel Univ, Dept Elect & Comp Engn, Philadelphia, PA 19104 USABaris Taskin - Drexel UniversityIEEE
- Publication Details
- 2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), pp.2595-2598
- Series
- IEEE International Symposium on Circuits and Systems
- Publisher
- IEEE
- Number of pages
- 4
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Identifiers
- 991019170361904721
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- Web of Science research areas
- Engineering, Electrical & Electronic