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Exploration of Segmented Bus As Scalable Global Interconnect for Neuromorphic Computing
Conference proceeding

Exploration of Segmented Bus As Scalable Global Interconnect for Neuromorphic Computing

Adarsha Balaji, Yuefeng Wu, Anup Das, Francky Catthoor, Siebren Schaafsma and Assoc Comp Machinery
GLSVLSI '19 - PROCEEDINGS OF THE 2019 ON GREAT LAKES SYMPOSIUM ON VLSI, pp 495-499
01 Jan 2019

Abstract

Computer Science Computer Science, Theory & Methods Science & Technology Technology
Spiking Neural Networks (SNNs) are efficient computation models for spatio-temporal pattern recognition on resource and power constrained platforms. Dedicated SNN hardware, also called neuromorphic hardware, can further reduce the energy consumption of these platforms. A neuromorphic hardware consists of crossbars, which are arrangements of input and output neurons with fully-connected synapses. Time-multiplexed interconnects are used to communicate spikes between crossbars. When a SNN model is mapped on multiple crossbars, the time-multiplexed interconnect increases spike latency and energy consumption, and disorders spike arrivals at output neurons, which reduces application accuracy. In this paper, we propose segmented bus interconnect for global synapses in a neuromorphic architecture. The objective is to reduce power consumption and enable parallel processing compared to traditional time-multiplexed interconnects. The fundamental idea for the segmented bus is to partition a single bus into several segments, with the segmentation switches controlled by software. We evaluate the scalability of segmented bus using synthetic applications. Our results show that segmented bus reduces the latency and energy consumption of the global synapse network significantly with respect to state-of-the-art techniques.

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Computer Science, Theory & Methods
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