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Conference proceeding
FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding
2009 IEEE International SOC Conference (SOCC), pp 423-426
Sep 2009
Abstract
Scalable video coding extension of H.264 standard is very suitable for content adaptation and addressing different terminals. However, in various cases it is necessary to perform transcoding in video coding layer requiring tremendous computation and hardware acceleration. In this paper, we present an efficient hardware architecture of a CAVLC codec based on a new method that provides a constant and reduced latency. The presented method calculates the 16 DCT coefficients in parallel. The results of hardware implementation targeting a Xilinx Virtex 5 FPGA are presented.
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2 citations in Scopus
Details
- Title
- FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding
- Creators
- M Guarisco - Nancy-UniversitéH Rabah - Nancy-UniversitéY Berviller - Nancy-UniversitéS Weber - Nancy-UniversitéS Belkouch - Cadi Ayyad University
- Publication Details
- 2009 IEEE International SOC Conference (SOCC), pp 423-426
- Publisher
- IEEE
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000277503200093
- Scopus ID
- 2-s2.0-77949640789
- Other Identifier
- 991019203655604721
InCites Highlights
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- Collaboration types
- Domestic collaboration
- International collaboration
- Web of Science research areas
- Engineering, Electrical & Electronic