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Fault-Tolerant Network Interface for Spatial Division Multiplexing Based Network-on-Chip
Conference proceeding

Fault-Tolerant Network Interface for Spatial Division Multiplexing Based Network-on-Chip

Anup Das, Akash Kumar and Bharadwaj Veeravalli
2012 7TH INTERNATIONAL WORKSHOP ON RECONFIGURABLE AND COMMUNICATION-CENTRIC SYSTEMS-ON-CHIP (RECOSOC)
01 Jan 2012

Abstract

Computer Science Computer Science, Theory & Methods Engineering Engineering, Electrical & Electronic Science & Technology Technology
The progressive maturity of VLSI manufacturing technology is helping in integrating more and more processing elements and memory units on a single die to form a Multiprocessor System-On-Chip (MPSoC). Network-on-Chip (NoC) is adopted as communication backbone for most of these modern day multiprocessor systems. As complexity of these system scales, there has been a growing concern on the dependability of these processing and communication elements. In this paper, we propose a centralized hardware fault-tolerant network interface (NI) for NoCs based on spatial division multiplexing. Experiments show that the proposed design has better throughput than a non fault-tolerant design with only 18% area overhead. We also introduce an area optimized distributed fault- tolerant NI architecture which provides 50% more throughput than the centralized design for high fault rates.

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Web of Science research areas
Computer Science, Theory & Methods
Engineering, Electrical & Electronic
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