Conference proceeding
From RTL to GDSII: An ASIC design course development using Synopsys® University Program
2011 IEEE International Conference on Microelectronic Systems Education, pp 72-75
Jun 2011
Abstract
The development of an ASIC design course using the Synopsys® University Program lectures, labs and tools is presented in this paper. The ASIC design course lasts for 20 weeks and the students learn the design flow using tools including Design Compiler™, IC Compiler™ and PrimeTime™. The syllabus is developed based on the Synopsys® University Program Curriculum. Besides the curriculum, the students are assigned projects to synthesize some small circuits to gain more in-depth knowledge about the ASIC design flow. A keystone project is assigned to facilitate the application of the entire IC physical design flow on an industrial size processor design.
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17 citations in Scopus
Details
- Title
- From RTL to GDSII: An ASIC design course development using Synopsys® University Program
- Creators
- Jianchao Lu - Drexel UniversityBaris Taskin - Drexel University
- Publication Details
- 2011 IEEE International Conference on Microelectronic Systems Education, pp 72-75
- Conference
- 2011 IEEE International Conference on Microelectronic Systems Education
- Publisher
- IEEE
- Number of pages
- 1
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Scopus ID
- 2-s2.0-79961138271
- Other Identifier
- 991019174015104721