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Generating FPGA-Accelerated DFT libraries
Conference proceeding   Open access

Generating FPGA-Accelerated DFT libraries

Paolo D'Alberto and Jeremy Russell Johnson
FCCM 2007: 15TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS, pp 173-184
01 Jan 2007
DOI: https://doi.org/10.1109/FCCM.2007.58
url
https://doi.org/10.1109/fccm.2007.58View
Published, Version of Record (VoR)Open Access (License Unspecified),  Open

Abstract

Computer Science Computer Science, Hardware & Architecture Computer Science, Information Systems Computer Science, Software Engineering Engineering Engineering, Electrical & Electronic Science & Technology Technology
We present a domain-specific approach to generate high-performance hardware-software partitioned implementations of the discrete Fourier transform (DFT) in fixed point precision. The partitioning strategy is a heuristic based on the DFT's divide-and-conquer algorithmic structure and fine tuned by the feedback-driven exploration of candidate designs. We have integrated this approach in the Spiral linear-transform code-generation framework to support push-button automatic implementation. We present evaluations of hardware-software DFT implementations running on the embedded PowerPC processor and the reconfigurable fabric of the Xilinx Virtex-11 Pro FPGA. In our experiments, the 1D and 2D DFT's FPGAaccelerated libraries exhibit between 2 and 7.5 times higher performance (operations per second) and up to 2.5 times better energy efficiency (operations per Joule) than the software-only version.

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17 citations in Web of Science
30 citations in Scopus

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Web of Science research areas
Computer Science, Hardware & Architecture
Computer Science, Information Systems
Computer Science, Software Engineering
Engineering, Electrical & Electronic
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