Conference proceeding
Hardware partitioning software for dynamically reconfigurable SoC design
3RD IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS
01 Jan 2003
Abstract
CAD tools support is essential in the success of today digital system design methodologies. Unfortunately, most of the classical design tools do not take into account the possibilities of reconfiguration that the FPGA component can offer. Here, we present a temporal hardware partitioning software, included in a design methodology, that uses the reconfiguration possibilities of the FPGA for the SOC system design. This automated partitioning tool minimises the number of cells needed to implement an application under a time constraint by taking into account the needs of bandwidth and memory size. This approach allows avoiding an oversizing of the implementation resource needs. It can also be useful for the design of a dynamically reconfigurable embedded device or system. We illustrate our approach in the real time image processing field.
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Details
- Title
- Hardware partitioning software for dynamically reconfigurable SoC design
- Creators
- P BrunetC TanougastY BervillerS Weber - Henri Poincaré University
- Contributors
- W Badawy (Editor)Y Ismail (Editor)
- Publication Details
- 3RD IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS
- Conference
- 3RD IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, 3rd
- Publisher
- IEEE
- Number of pages
- 6
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000184335100022
- Scopus ID
- 2-s2.0-47349111370
- Other Identifier
- 991019203639504721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Computer Science, Hardware & Architecture
- Computer Science, Theory & Methods