Conference proceeding
High-Performance, Low-Power Resonant Clocking Embedded Tutorial
2012 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), pp.742-745
ICCAD-IEEE ACM International Conference on Computer-Aided Design
01 Jan 2012
Abstract
Clock distribution networks consume a significant portion of on-chip power. Traditional buffered clock distribution power is limited by frequency, capacitance, and activity rates. Resonant clock distributions can reduce this power by "recycling" energy on-chip and reducing the overall clock power. This tutorial introduces recent techniques for distributed-LC, traveling wave, and standing wave resonant clock distributions. In particular, the tutorial discusses the recent developments and open research problems. The tutorial covers both circuits, computer-aided design algorithms and methodologies for resonant clocking.
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Details
- Title
- High-Performance, Low-Power Resonant Clocking Embedded Tutorial
- Creators
- Matthew R. Guthaus - Univ Calif Santa Cruz, Dept Comp Engn, Santa Cruz, CA 95064 USABaris Taskin - Drexel UniversityIEEE
- Publication Details
- 2012 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), pp.742-745
- Series
- ICCAD-IEEE ACM International Conference on Computer-Aided Design
- Publisher
- IEEE
- Number of pages
- 4
- Grant note
- CCF-1053838; CCF-0845270 / National Science Foundation; National Science Foundation (NSF)
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Identifiers
- 991019170375704721
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