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High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design
Conference proceeding

High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design

Can Sitik, Leo Filippini, Emre Salman, Baris Taskin and IEEE
2014 IEEE Computer Society Annual Symposium on VLSI, pp 498-503
Jul 2014
DOI: https://doi.org/10.1109/ISVLSI.2014.53

Abstract

CAD Capacitance clock tree Clocks Delays low swing Power demand Synchronization timing Wires
Low swing clocking is a low power design methodology that scales the clock voltage to decrease power consumption of the clock distribution networks, with an expected degradation in the performance. In this work, a novel low swing clock tree synthesis methodology is combined with a custom low swing clock-aware D flip-flop (DFF) design. The low swing clocking serves to reduce the power dissipation whereas the custom low swing-aware DFF serves to preserve the performance of the IC. The experimental results performed on the three largest circuits of ISCAS'89 benchmarks operating at 1GHz in the 32nm technology show that the proposed methodology can achieve an average of 16% power savings in the clock tree compared to its full swing counterpart, while satisfying the same clock skew (50ps) and slew (150ps) constraints at the worst case corner of operation. Moreover, the clock-to-output delay of the low swing DFF does not increase compared to traditional full swing DFF, while consuming only 1% more power.

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3 citations in Web of Science
8 citations in Scopus

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Collaboration types
Domestic collaboration
Web of Science research areas
Computer Science, Hardware & Architecture
Computer Science, Theory & Methods
Engineering, Electrical & Electronic
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