Conference proceeding
Improving Scalability of NoC-Based Neuromorphic Hardware with Compressed AER (C-AER) Protocol
IEEE International Symposium on Circuits and Systems proceedings, pp 1-5
25 May 2025
Abstract
Digital neuromorphic architectures use the address event representation protocol (AER), which encodes a spike into the address of it's originating neuron. We show that, this baseline AER protocol is inefficient in network-on-chip (NoC)-based many-core designs, increasing the congestion, delay and energy consumption on the NoC. We introduce CAERPRO, a novel spike encoding protocol for many-core neuromorphic hardware. The key idea of CAERPRO is to organize the output spikes of a core (in space and time) as a single binary spike string and compress it into fewer bits using a static compression technique. We implement CAERPRO for a state-of-the-art NoC-based neuromorphic hardware and synthesize it using Synopsys Design compiler in 32nm technology. Our results using 4 workloads show that, compared to baseline AER protocol, CAERPRO reduces energy consumption on the NoC by an average 14.8× and latency of spike events by an average 9.6×. Furthermore, we show that CAERPRO compression and decompression hardware consume only 2.97% of the total power of a neuromorphic core at 1Mhz clock frequency and introduce a marginal area overhead of 0.26%.
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Details
- Title
- Improving Scalability of NoC-Based Neuromorphic Hardware with Compressed AER (C-AER) Protocol
- Creators
- Arghavan Mohammadhassani - Drexel UniversitySarah Johari - Drexel UniversityKrupa Tishbi - Drexel UniversityAnup Das - Drexel University
- Publication Details
- IEEE International Symposium on Circuits and Systems proceedings, pp 1-5
- Publisher
- IEEE
- Grant note
- Accenture (10.13039/100004672)
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering; Computer Science (Computing); College of Engineering
- Scopus ID
- 2-s2.0-105010576770
- Other Identifier
- 991022061054104721