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Increasing the SAT Attack Resiliency of In-Cone Logic Locking
Conference proceeding

Increasing the SAT Attack Resiliency of In-Cone Logic Locking

Kyle Juretus, Ioannis Savidis and IEEE
2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), v 2019-
01 Jan 2019
DOI: https://doi.org/10.1109/ISCAS.2019.8702683

Abstract

Engineering Engineering, Electrical & Electronic Science & Technology Technology
A method to increase the resiliency of in-cone logic locking against the SAT attack is described in this paper. Current logic locking techniques provide protection through the addition of circuitry outside of the original logic cone. While the additional circuitry provides provable security against the SAT attack, other attacks, such as the removal attack, limit the efficacy of such techniques. Traditional in-cone logic locking is not prone to removal attacks, but is less secure against the SAT attack. The focus of this paper is, therefore, the analysis of in-cone logic locking to increase the security against the SAT attack, which provides a comparison between in-cone techniques and newly developed methodologies. A novel algorithm is developed that utilizes maximum fanout free cones (MFFC). The application of the algorithm limits the fanout of incorrect key information. The MFFC based algorithm resulted in an average increase of 61.8% in the minimum number of iterations required to complete the SAT attack across 1,000 different variable orderings of the circuit netlist while restricted to a 5 % overhead in area.

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4 citations in Web of Science
10 citations in Scopus

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Engineering, Electrical & Electronic
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