Conference proceeding
Incremental Register Placement for Low Power CTS
2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009)
01 Jan 2009
Abstract
An incremental register placement algorithm within clock tree synthesis (CTS) is presented for low power system design. The method places registers together while generating the clock tree and hence is able to reduce clock tree wirelength. The increase in the logic wirelength is limited since the registers are moved within a small distance. The skew requirement of the clock tree can be strictly maintained as the limited register placement is integrated into the CTS algorithm. Experimental results show that the clock tree wirelength can be reduced by an average of 2.8% compared to the clock tree generated by BST/DME algorithm with a fanout factor of 2. The power consumption of this system is 1.1% less than that of a system with clock tree generated by BST/DME algorithm. Higher improvement can be achieved for higher fanout factors on a clock tree.
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Details
- Title
- Incremental Register Placement for Low Power CTS
- Creators
- Jianchao Lu - Drexel UniversityBans Taskin - Drexel UniversityIEEE
- Publication Details
- 2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009)
- Conference
- 2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009)
- Publisher
- IEEE
- Number of pages
- 5
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000290246700058
- Scopus ID
- 2-s2.0-77951487432
- Other Identifier
- 991019203361004721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Computer Science, Hardware & Architecture
- Engineering, Electrical & Electronic