Conference proceeding
Linear timing analysis of SOC synchronous circuits with level-sensitive latches
15th Annual IEEE International ASIC/SOC Conference, v 2002-, pp 358-362
2002
Abstract
This paper describes a linear programming (LP) formulation applicable to the timing analysis of large scale SOC synchronous circuits with level-sensitive latches. The proposed formulation uses a variation of the big M method (W. L. Winston, Operations Research Application and Algorithms, PWS-Kent Publ. Co., 2nd ed., 1991) to modify the nonlinear constraints in the problem formulation into solvable linear constraints. By making maximum use of cycle stealing (I. Lin et al, Proc. 29th ACM/IEEE Design Automation Conf., pp. 393-398, 1992), operation at a higher clock frequency (reduced clock period) is possible. The industrial LP solver CPLEX is used on the ISCAS'89 benchmark circuits, demonstrating significant improvements in clock period.
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Details
- Title
- Linear timing analysis of SOC synchronous circuits with level-sensitive latches
- Creators
- B Taskin - University of PittsburghI.S Kourtev - University of Pittsburgh
- Publication Details
- 15th Annual IEEE International ASIC/SOC Conference, v 2002-, pp 358-362
- Publisher
- IEEE
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000179659500063
- Scopus ID
- 2-s2.0-1342315485
- Other Identifier
- 991019203636504721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Computer Science, Software Engineering
- Engineering, Electrical & Electronic