Logo image
Back
Load balanced on-chip power delivery for average current demand
Conference proceeding

Load balanced on-chip power delivery for average current demand

Divya Pathak, Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana, Houman Homayoun, Ioannis Savidis and IEEE
2016 International Great Lakes Symposium on VLSI (GLSVLSI), v 18-20-, pp 439-444
May 2016
DOI: https://doi.org/10.1145/2902961.2903030

Abstract

Benchmark testing Phasor measurement units Power demand Regulators Switches System-on-chip Voltage control
A dynamic power management system for homogeneous chip multi-processors (CMP) is proposed. Each core of the CMP includes on chip DC-DC switching buck converters that are interconnected through a switch network. The peak current rating of the buck converter is selected to meet only the average current demand of the load circuit. A real-time load balancing algorithm is developed which reconfigures the power delivery network by combining the output of multiple buck converters when the workload demand exceeds the peak current rating. Simulation results for the proposed power delivery method indicate up to a 44% reduction in the energy consumption of the CMP system. In addition, the on-chip footprint of the power delivery network, including the on-chip voltage regulators and the switching network, is reduced by at least 23%.

Metrics

10 Record Views
3 citations in Web of Science
3 citations in Scopus

Details

InCites Highlights

Data related to this publication, from InCites Benchmarking & Analytics tool:

Collaboration types
Domestic collaboration
Web of Science research areas
Computer Science, Hardware & Architecture
Computer Science, Theory & Methods
Logo image