Conference proceeding
Low Voltage Clock Tree Synthesis with Local Gate Clusters
GLSVLSI '19 - PROCEEDINGS OF THE 2019 ON GREAT LAKES SYMPOSIUM ON VLSI, pp 99-104
01 Jan 2019
Abstract
In this paper, a novel local clock gate cluster-aware low voltage clock tree synthesis methodology is introduced. In low voltage/swing clocking, timing closure is a challenging problem due to tight skew and slew constraints. The clock gating makes this problem more challenging due to the high delay mismatch between the gated and the non-gated sinks. The proposed methodology preserves the power savings of the clock gating and exploits low swing clocking to further reduce the power consumption, while maintaining the same skew and slew constraints as the full swing counterpart. Experimental results performed on the large circuits of ISCAS'89 benchmarks operating at 1.5GHz in the 45nm technology node demonstrate that the proposed methodology can provide 38% power savings as compared to a full swing gated clock tree, achieving an additional 12% savings as compared to a low swing non-gated clock tree.
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Details
- Title
- Low Voltage Clock Tree Synthesis with Local Gate Clusters
- Creators
- Can Sitik - Drexel UniversityWeicheng Liu - Stony Brook UniversityBaris Taskin - Drexel UniversityEmre Salman - Stony Brook UniversityAssoc Comp Machinery
- Publication Details
- GLSVLSI '19 - PROCEEDINGS OF THE 2019 ON GREAT LAKES SYMPOSIUM ON VLSI, pp 99-104
- Series
- Proceedings - Great Lakes Symposium on VLSI
- Publisher
- Assoc Computing Machinery
- Number of pages
- 6
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000474339800020
- Scopus ID
- 2-s2.0-85082615821
- Other Identifier
- 991019168890804721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Collaboration types
- Domestic collaboration
- Web of Science research areas
- Computer Science, Theory & Methods