Conference proceeding
Multi-Voltage Domain Clock Mesh Design
2012 IEEE 30TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD)
01 Jan 2012
Abstract
This paper investigates the effectiveness of a multi-voltage clock network design that is built using the mesh topology. Unlike a clock tree, a single clock mesh that spans multiple voltage domains is infeasible due to the incompatibility of voltage levels of the clock drivers on the electrically-shorted mesh-each voltage domain requires a separate mesh. These disjoint meshes need to be matched in clock skew between the domains. In addition, the additional power dissipation of the level shifters in the logic needs to be compared against the power savings of multi-voltage domain implementation. The case study performed with the largest ISCAS'89 benchmark circuits operating at 500 MHz, 90 nm technology concludes two important results that highlight the benefits of multi-voltage clock mesh design: 1) The multi-voltage domain clock mesh can achieve 37.14% lower power with a 9 ps increase in clock skew over the single-voltage domain clock mesh, and 2) The multi-voltage domain clock mesh achieves 66 ps less skew with a 20.92% increase in power dissipation over a multi-voltage domain clock tree.
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Details
- Title
- Multi-Voltage Domain Clock Mesh Design
- Creators
- Can Sitik - Drexel UniversityBaris Taskin - Drexel UniversityIEEE
- Publication Details
- 2012 IEEE 30TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD)
- Series
- Proceedings IEEE International Conference on Computer Design
- Publisher
- IEEE
- Number of pages
- 6
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000316948500035
- Scopus ID
- 2-s2.0-84872071276
- Other Identifier
- 991019173764704721
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- Web of Science research areas
- Computer Science, Hardware & Architecture
- Engineering, Electrical & Electronic