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Noise Constrained Optimum Selection of Supply Voltage for IoT Applications
Conference proceeding

Noise Constrained Optimum Selection of Supply Voltage for IoT Applications

Shazzad Hossain, Ioannis Savidis and IEEE
2018 IEEE International Symposium on Circuits and Systems (ISCAS), v 2018-, pp 1-5
May 2018

Abstract

Integrated circuit modeling Inverters Logic gates Optimization Semiconductor device modeling SPICE Threshold voltage
An optimization technique is proposed to set the supply voltage of an integrated circuit for a given range of threshold voltages. The algorithm accounts for the variations in maximum operating frequency f max , noise margins, and threshold voltage. The algorithmically determined supply and threshold voltages are compared with SPICE simulation for a 130 nm CMOS technology, where per cent error of up to 14% and 8% are observed for, respectively, the average noise margins NM avg and f max as compared to target circuit specifications for noise margin and frequency. The evaluated ranges of the supply and threshold voltages are, respectively, 200 mV ≤ V dd ≤ 1200 mV and 250 mV ≤ V t ≤ 700 mV. The technique is applied to both a 130 nm and 45 nm CMOS technology and results of noise margin and frequency are compared through SPICE simulation. The 45 nm technology node exhibits variation of up to 0.89× and 4.3× in, respectively, NM avg and f max as compared to an inverter in a 130 nm technology.

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Engineering, Electrical & Electronic
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