Conference proceeding
Optimal reconfigurable HW/SW co-design of load flow and optimal power flow computation
2006 POWER ENGINEERING SOCIETY GENERAL MEETING, VOLS 1-9, 1409
01 Jan 2006
Featured in Collection : UN Sustainable Development Goals @ Drexel
Abstract
Load flow and Optimal Power Flow (OPF) constitute core computations used in energy market operation. We considered different design partitions of computational tasks for a desktop computer equipped with Field Programmable Gate Array (FPGA). Load flow and OPF require Lower-Upper triangular matrix decomposition (LU). The number of clock cycles required for data transfer and floating-point operations were used as performance measures in determining optimal hardware/software partitions for each problem. Optimal partition performance is achieved by assigning the Lower-Upper triangular decomposition (LU) and matrix multiplication operations to custom hardware cores. A comparison between the proposed partition and software implemented using a state-of-the-art sparse matrix package running on a 3.2 GHz Pentium 4 shows a six-fold speedup.
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Details
- Title
- Optimal reconfigurable HW/SW co-design of load flow and optimal power flow computation
- Creators
- M. MurachP. VachranukunkietP. NagvajaraJ. JohnsonC. NwankpaIEEE
- Publication Details
- 2006 POWER ENGINEERING SOCIETY GENERAL MEETING, VOLS 1-9, 1409
- Conference
- 2006 POWER ENGINEERING SOCIETY GENERAL MEETING
- Series
- IEEE Power Engineering Society General Meeting
- Publisher
- IEEE
- Number of pages
- 2
- Grant note
- CH11171 / United States Department of Energy (DOE)
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Identifiers
- 991019170471804721
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- Energy & Fuels