Conference proceeding
Performance improvement of edge-triggered sequential circuits
Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004, pp 607-610
2004
Abstract
The paper presents a novel delay insertion method to improve the performance of edge-triggered sequential circuits through clock skew scheduling. Clock skew scheduling (CSS) is performed on synchronous circuits in order to increase the maximum operating frequency. With CSS, the original circuit topology is preserved while the clock distribution network is modified to satisfy an optimal clock skew schedule. The paper proposes a circuit modification technique consisting of delay insertion into logic paths in order to improve the minimum possible clock period. In experiments, improvements of up to 90% are observed over the zero clock skew, flip-flop based circuits for the selected ISCAS'89 suite of benchmark circuits.
Metrics
2 Record Views
Details
- Title
- Performance improvement of edge-triggered sequential circuits
- Creators
- B Taskin - University of PittsburghI.S Kourtev - University of PittsburghIEEE
- Publication Details
- Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004, pp 607-610
- Conference
- 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004, 11th
- Publisher
- IEEE
- Number of pages
- 1
- Resource Type
- Conference proceeding
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Web of Science ID
- WOS:000228424500156
- Other Identifier
- 991019203320604721
InCites Highlights
Data related to this publication, from InCites Benchmarking & Analytics tool:
- Web of Science research areas
- Computer Science, Hardware & Architecture
- Engineering, Electrical & Electronic